1. Field of the Invention
The present invention relates to a power converter formed of HVIC (high voltage integrated circuit), and particularly to a power semiconductor device having a function of simultaneously controlling both p-side and n-side driving power devices.
2. Related Art
FIG. 10 shows a circuit diagram of a motor driving inverter, which is classic as a power converter circuit, and basic operations thereof will be described hereinafter. Power devices (17, 18, 19, 20, 21, and 22) for respective U, V, and W phases are connected between a p-side (high voltage side) and an n-side (low voltage side) of an inverter-driving power source 23. FWDs (Free Wheel Diodes) 31, 32, 33, 34, 35, and 36 are connected parallel to the respective power devices. Input signal processor circuits (2, 3, and 4) are connected to a control signal generator circuit 1 such as a microcomputer that generates control signals for the respective power devices. A power source 30 feeds the input signal processor circuits.
Power-device driving circuits (11, 12, 13, 14, 15, and 16) and dedicated power sources (24, 25, 26, 27, 28, and 29) for driving the power devices are connected for the respective phases. Since a GND potential in the input signal processor circuit and the power device driving circuit are different from each other, photocouplers (5, 6, 7, 8, 9, and 10) is used to couple them.
In the practical inverter, the p-side power devices (17, 19, and 21) and the n-side power devices (18, 20, and 22) for the respective U, V, and W phases are controlled to perform switching according to a driving method. Thereby, motor control is implemented.
FIG. 11 shows an example of inverter circuit using HVICs in accordance with the circuit diagram shown in FIG. 10. The HVICs are individually formed to include input signal processor circuits (2 to 4), power device driving circuits (11 to 16), and level shift circuits (37, 38, and 39) each having a function equivalent to a photocoupler. In addition, the example as shown is configured to include one-chip integrated circuits (50, 51, and 52) for the respective U, V, and W phases.
The inverter formed of the HVIC has advantages that the reliability of the circuit can be enhanced by incorporating the level shift into the chip when compared to the inverter using the photocouplers, and that more inexpensive system can be provided by reducing the number of power sources and the number of components mounted on the inverter.
As shown in FIG. 11, the circuit using only the external power source 30 as a drive power source requires only the following additional components: bootstrap diodes (40, 41, and 42) and bootstrap capacitors (43, 44, and 45) provided as power sources that power the driving circuits (11, 13, and 15) for the p-side power devices (17, 19, and 21) for the respective phases.
FIG. 12 shows a schematic view of an inverter circuit using HVICs. The circuit is shown as an example in which control signals are transmitted from an inverter-driving control signal generator circuit to respective HVICs (50, 51, and 52) in U, V, and W phases to drive power devices (17, 18, 19, 20, 21, and 22). In this circuit configuration, GNDs of the respective HVICs (50 to 52) and emitter terminals of the respective power devices (18, 20, 22) are connected in each of the U, V, and W phases. L1 to L12 denote parasitic inductances as described later.
FIG. 13 shows an example of substrate with the circuit shown in FIG. 12 being.mounted thereon. In an inverter circuit, standard values such as a voltage between P and N, a power device current rating and the like differ in accordance with the application. However, generally, the operation of the inverter circuit processing high voltages and high currents is implemented through high-speed switching performed using power devices. As such, it is strongly demanded that power loss in the inverter itself is reduced to become as small as possible. Ordinarily, the power loss is discharged to the outside of the inverter as joule heat.
In the configuration shown in FIG. 13, the emitter of the power device 18 in the U phase is connected to the GND of the HVIC and the anode of an FWD (32) via a bonding wire. It is further connected to an n-electrode (54) of a path bar (PB) through a bonding wire via the anode of the FWD (32). Losses in the inverter circuit can be categorized into two types, which are a DC loss and a switching loss.
The DC loss consists of a loss occurring with the power device and a loss occurring with a wire such as a bonding wire. The loss occurring with the power device is caused by current regularly flowing from the p-electrode to the n-electrode via the p-side power device, the load (inductance), and the n-side power device.
FIG. 14 shows a current path that causes the loss in the power device. Since the loss in the wire or the like is determined depending on the current and the electric resistance, the wire electric resistance needs to be reduced lower as the current increases higher.
The switching loss is the sum of a loss occurring with the power device when the power device turns from ON to OFF and turns from OFF to ON. Generally, the power device loss increases as the switching speed increases and as the voltage between P and N decreases. For this reason, the reduction in the loss plays an important role when the inverter circuit is used in a high-voltage and high-current region; hence, various improvements are continually made for the power device, particularly, in order to improve switching speed.
The path bar causes a part of loss occurring in the inverter. As such, the path bar needs to be shaped as thick and short as possible to reduce the electric resistance. However, the power device or other components, having a minimum size necessary to assure the rated current, need to be mounted on a package. In consideration of the above, generally, the shape as shown in FIG. 13 can be considered.
In the n-electrode (54), parasitic inductors exist, as shown with reference symbols L7 and L8. In addition, the parasitic inductors shown with reference symbols L1, L2, L3, L4, L5, and L6 exist in wire bonds between the power devices, the FWDs, and path bars (PB). Moreover, between a point A, a point B, and a point C of respective GND nodes of the U-phase, V-phase, W-phase driving HVICs (50, 51, and 52), there exist the parasitic inductances L9, L10, and L11 formed in wire bonds from GND terminals of the respective HVICs to emitter terminals of the HVICs and wiring patterns of a substrate (55). Furthermore, there exist the parasitic inductance L12 (between the U phase and the V phase) and a parasitic inductance L13 (between the V phase and the W phase) that are formed with wiring patterns connecting between the GND terminals of the respective HVICs.
When the inverter operation is performed in the circuit shown in FIG. 12, a malfunction can occur because of the parasitic inductances L1 to L13. Hereinafter, mechanism of the malfunction occurrence will be described with reference to FIGS. 14 and 15.
Referring to FIG. 14, the U-phase p-side power device (17) and the V-phase n-side power device (20) are in the ON state, and a current flows through a path shown by arrows. Then, as shown in FIG. 15, even after the U-phase p-side power device (17) has turned OFF from the ON state, the current is caused by energy stored in a load (60) of an inductance to keep flowing. Meanwhile, the U-phase n-side power device (18) is in the OFF state. In this case, however, since the FWD (32) connected parallel to the n-side power device (18) is in a forward-biased state with respect to the current, the current flows through the path in the following: load (60)xe2x86x92V-phase n-side power device (20)xe2x86x92n-electrode parasitic inductance (L7)xe2x86x92U-phase n-side FWD (32)xe2x86x92load (60). In addition, as can be seen by comparing FIG. 15 with FIG. 12, current is also flowing to the parasitic inductances L1, L2, L3, L4, L9, L10, and L12.
In the above case, a voltage V expressed in the following formula is generated in each of the inductances L:
V=Lxc3x97(di/dt)(where xe2x80x9cdi/dtxe2x80x9d=current variation ratio)
Accordingly, a potential difference is occurring between the point A of the GND node of the U-phase driving HVIC (50) and the point B of the GND node of the V-phase driving HVIC (51), which are shown in FIG. 12. Digital control signals are transmitted to the HVICs (50 to 52) in the respective phases from the control signal generator circuit (1) shown in FIG. 12. However, because of the variations in the GND potential as described above, a case can occur in which the HVICs (50 to 52) in the respective phases erroneously recognize the control signals, thereby causing a malfunction.
The present invention provides a power semiconductor device capable of operating without causing erroneous recognition of control signals that can occur because of variations in ground potential.
The power semiconductor device includes an input signal processor circuit to which control signals are input, and power device driving circuits for driving power devices. Level shift circuits are individually inserted between the input signal processor circuit and the power device driving circuit on a p-side and between the input signal processor circuit and the power device driving circuit on an n-side to electrically insulate ground lines for the p-side and n-side power device driving circuits and a ground line for the input signal processor circuit.